Altera cyclone V Technical Reference page 1449

17-234
SGMII_RGMII_SMII_Control_Status
Offset:
0xD8
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
SGMII_RGMII_SMII_Control_Status Fields
Bit
3
lnksts
2:1
lnkspeed
0
lnkmod
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
This bit indicates whether the link is up (1'b1) or
down (1'b0).
0x0
0x1
This bit indicates the current speed of the link. Bit 2 is
reserved when the MAC is configured for the SMII
PHY interface.
Value
0x0
0x1
0x2
This bit indicates the current mode of operation of the
link
0x0
0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Value
Linkdown
Linkup
Description
Link Speed 2.5MHz
Link Speed 25MHz
Link Speed 125MHz
Value Description
Half Duplex
Full Duplex
21 20 19 18
5 4 3
lnkst lnkspeed
s
RO
0x0
Description
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
2 1 0
lnkmod
RO 0x0 RO 0x0
Access Reset
RO 0x0
RO 0x0
RO 0x0
Send Feedback