Altera cyclone V Technical Reference page 1451

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When low and bit 4 is set, all MMC counters get

preset to almost-half value. All octet counters get

preset to 0x7FFF_F800 (half - 2KBytes) and all frame-

counters gets preset to 0x7FFF_FFF0 (half - 16).

When this bit is high and bit 4 is set, all MMC

counters get preset to almost-full value. All octet

counters get preset to 0xFFFF_F800 (full - 2KBytes)

and all frame-counters gets preset to 0xFFFF_FFF0

(full - 16). For 16-bit counters, the almost-half preset

values are 0x7800 and 0x7FF0 for the respective octet

and frame counters. Similarly, the almost-full preset

values for the 16-bit counters are 0xF800 and 0xFFF0.

When this bit is set, all counters are initialized or

preset to almost full or almost half according to bit 5.

This bit is cleared automatically after 1 clock cycle.

This bit, along with bit 5, is useful for debugging and

testing the assertion of interrupts because of MMC

counter becoming half-full or full.

When this bit is set, it freezes all MMC counters to

their current value. Until this bit is reset to 0, no

MMC counter is updated because of any transmitted

or received frame. If any MMC counter is read with

the Reset on Read bit set, then that counter is also

cleared in this mode.

Preset All Counters to almost-half

Present All Counters almost-full

Counters not preset

Counters preset to full or almost full

Update MMC Counters

Freeze MMC counters to current value

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