Altera cyclone V Technical Reference page 1457

Hard processor system
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17-242
MMC_Receive_Interrupt
Bit
6
rxalgnerfis
5
rxcrcerfis
4
rxmcgfis
3
rxbcgfis
2
rxgoctis
1
rxgboctis
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Name
This bit is set when the rxalignmenterror counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxcrcerror counter reaches
half of the maximum value or the maximum value.
Value
0x0
0x1
This bit is set when the rxmulticastframes_g counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxbroadcastframes_g counter
reaches half of the maximum value or the maximum
value.
This bit is set when the rxoctetcount_g counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxoctetcount_bg counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
Description
Description
rxalignmenterror < half max
rxalignmenterror >= half max
Description
rxcrcerror < half max
rxcrcerror >= half max
Description
rxbroadcastframes_g < half max
rxbroadcastframes_g >= half max
Description
Rxoctetcount_g < half max
Rxoctetcount_g >= half max
Description
Rxoctetcount_bg < half max
Rxoctetcount_bg >= half max
2016.10.28
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RO
0x0
RO
0x0
RO
0x0
RO
0x0
RO
0x0
RO
0x0
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