Altera cyclone V Technical Reference page 1452

Hard processor system

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MMC_Receive_Interrupt

The MMC Receive Interrupt register maintains the interrupts that are generated when the following

happens: * Receive statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter

and 0x8000 for 16-bit counter). * Receive statistic counters cross their maximum values (0xFFFF_FFFF for

32-bit counter and 0xFFFF for 16-bit counter). When the Counter Stop Rollover is set, then interrupts are

set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide register. An

interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least

significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Ethernet Media Access Controller

Send Feedback

When this bit is set, the MMC counters are reset to

zero after Read (self-clearing after reset). The counters

are cleared when the least significant byte lane

(bits[7:0]) is read.

When this bit is set, after reaching maximum value,

the counter does not roll over to zero.

When this bit is set, all counters are reset. This bit is

cleared automatically after one clock cycle.

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

No reset after read

Reset after read

Counter Roll Over

Counter does not Roll Over

Auto cleared after 1 clock cycle

All Counters Reset

Base Address

MMC_Receive_Interrupt

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