Altera cyclone V Technical Reference page 1455

Hard processor system
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17-240
MMC_Receive_Interrupt
Bit
16
rx1024tmaxoctgbfis
15
rx512t1023octgbfis
14
rx256t511octgbfis
13
rx128t255octgbfis
12
rx65t127octgbfis
Altera Corporation
Name
This bit is set when the rx1024tomaxoctets_gb
counter reaches half of the maximum value or the
maximum value.
Value
0x0
0x1
This bit is set when the rx512to1023octets_gb counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rx256to511octets_gb counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rx128to255octets_gb counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This is set when the rx65to127octets_gb counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
Description
Description
rx1024tomaxoctets_gb < half max
rx1024tomaxoctets_gb >= half max
Description
rx512to1023octets_gb < half max
rx512to1023octets_gb >= half max
Description
rx256to511octets_gb < half max
rx256to511octets_gb >= half max
Description
rx128to255octets_gb < half max
rx128to255octets_gb >= half max
Description
rx65to127octets_gb < half max
rx65to127octets_gb >= half max
2016.10.28
Access
Reset
RO
0x0
RO
0x0
RO
0x0
RO
0x0
RO
0x0
Ethernet Media Access Controller
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cv_5v4

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