Altera cyclone V Technical Reference page 1450

cv_5v4
2016.10.28
MMC_Control
The MMC Control register establishes the operating mode of the management counters. Note: The bit 0
(Counters Reset) has higher priority than bit 4 (Counter Preset). Therefore, when the Software tries to set
both bits in the same write cycle, all counters are cleared and the bit 4 is not set.
Module Instance
emac0
emac1
Offset:
0x100
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
MMC_Control Fields
Bit
8
ucdbc
Ethernet Media Access Controller
Send Feedback
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
When set, this bit enables MAC to update all the
related MMC Counters for Broadcast frames dropped
due to setting of DBF bit (Disable Broadcast Frames)
of MAC Filter Register at offset 0x0004. When reset,
MMC Counters are not updated for dropped
Broadcast frames.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
ucdbc Reserved
RW
0x0
Description
MMC_Control
Register Address
0xFF700100
0xFF702100
21 20 19 18
5 4 3 2
cntpr cntpr cntfr rston
stlvl st eez rd
RW RW RW RW
0x0 0x0 0x0 0x0
Access
17-235
17 16
1 0
cntst cntrst
opro
RW 0x0
RW
0x0
Reset
RW 0x0
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