Altera cyclone V Technical Reference page 1454

Hard processor system
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cv_5v4
2016.10.28
Bit
21
rxfovfis
20
rxpausfis
19
rxorangefis
18
rxlenerfis
17
rxucgfis
Ethernet Media Access Controller
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Name
This bit is set when the rxfifooverflow counter reaches
half of the maximum value or the maximum value.
Value
0x0
0x1
This bit is set when the rxpauseframe counter reaches
half of the maximum value or the maximum value.
Value
0x0
0x1
This bit is set when the rxoutofrangetype counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxlengtherror counter reaches
half of the maximum value or the maximum value.
Value
0x0
0x1
This bit is set when the rxunicastframes_gb counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
Description
Description
rxfifooverflow < half max
rxfifooverflow >= half max
Description
rxpauseframe < half max
rxpauseframe >= half max
Description
rxoutofrangetype < half max
rxoutofrangetype >= half max
Description
rxlengtherror < half max
rxlengtherror >= half max
Description
rx1024tomaxoctets_gb < half max
rx1024tomaxoctets_gb >= half max
MMC_Receive_Interrupt
Access
RO
RO
RO
RO
RO
Altera Corporation
17-239
Reset
0x0
0x0
0x0
0x0
0x0

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