Altera cyclone V Technical Reference page 1453

17-238
MMC_Receive_Interrupt
31 30
Reserved
15 14
rx512t10 rx256 rx128
23octgbf t511o t255o
is ctgbf ctgbf
is
RO 0x0
RO
0x0
MMC_Receive_Interrupt Fields
Bit
25
rxctrlfis
24
rxrcverrfis
23
rxwdogfis
22
rxvlangbfis
Altera Corporation
29 28 27 26
13 12 11 10
rx65t rx64o rxosi
127oc ctgbf zegfi
tgbfi is s
is s
RO RO
RO RO 0x0 0x0
0x0 0x0
Name
This bit is set when the rxctrlframes_g counter
reaches half of the maximum value or the maximum
value.
This bit is set when the rxrcverror counter reaches
half of the maximum value or the maximum value.
This bit is set when the rxwatchdogerror counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxvlanframes_gb counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
Bit Fields
25 24 23 22
rxctr rxrcv rxwdo rxvla
lfis errfi gfis ngbfi
s s
RO RO
0x0 RO 0x0 RO
0x0 0x0
9 8 7 6
rxusi rxjab rxrun rxalg
zegfi erfis tfis nerfi
s s
RO RO
RO 0x0 0x0 RO
0x0 0x0
Description
Description
rxwatchdogerror < half max
rxwatchdogerror >= half max
Description
rxvlanframes_gb < half max
rxvlanframes_gb >= half max
21 20 19 18
rxfov rxpau rxora rxlen
fis sfis ngefi erfis
s
RO RO RO
0x0 0x0 RO 0x0
0x0
5 4 3 2
rxcrc rxmcg rxbcg rxgoc
erfis fis fis tis
RO RO RO RO
0x0 0x0 0x0 0x0
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
rxucg rx1024tm
fis axoctgbf
is
RO
0x0 RO 0x0
1 0
rxgbo rxgbfrmi
ctis s
RO RO 0x0
0x0
Access Reset
RO 0x0
RO 0x0
RO 0x0
RO 0x0
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