Sd/Mmc Controller Block Diagram And System Integration; Functional Description Of The Sd/Mmc Controller - Altera Cyclone V Device Handbook

cv_54011
2013.12.30
Max Clock
Card Device
Type
eMMC 50

SD/MMC Controller Block Diagram and System Integration

The SD/MMC controller includes a bus interface unit (BIU) and a card interface unit (CIU). The BIU
provides a slave interface for a host to access the control and status registers (CSRs). Additionally, this unit
also provides independent FIFO buffer access through a DMA interface. The DMA controller is responsible
for exchanging data between the system memory and FIFO buffer. The DMA registers are accessible by the
host to control the DMA operation. The CIU supports the SD, MMC, and CE-ATA protocols on the controller,
and provides clock management through the clock control block. The interrupt control block for generating
an interrupt connects to the generic interrupt controller in the ARM
(MPU) subsystem.
Figure 11-1: SD/MMC Controller Connectivity
MPU
Subsystem

Functional Description of the SD/MMC Controller

This section describes the SD/MMC controller components and how the controller operates.
(30)
SPI mode is obsolete in the MMC 4.41 specification.
SD/MMC Controller
Send Feedback
Voltages
Max Data
Supported
Speed Rate
3.3 V
(MHz) (MBps)
25 √
Bus Interface Unit
Master
DMA
Interface
Controller
Slave
Register
Interface
Block
Interrupt
Control
SD/MMC Controller Block Diagram and System Integration
Bus Modes Supported
(30)
1.8 V SPI 1 bit 4 bit
√ √ √
SD/MMC Controller
FIFO
Synchronizer
Buffer
Control
Storage
FIFO Buffer
Bus Speed Modes
Supported
8 bit Default High Speed
Speed
√ √ √
® ™
Cortex -A9 microprocessor unit
Card Interface Unit
Data Path
Control
FIFO
Command
Buffer
Path Control
Control
Clock
Control
11-3
Card Bus I/O Pins
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