Axi-Exclusive Support; Memory Protection - Altera Cyclone V Device Handbook

cv_54008
2013.12.30
Figure 8-6: Bank Interleave With Chip Select Interleave Address Decoding

AXI-Exclusive Support

The single-port controller supports AXI-exclusive operations. The controller implements a table shared
across all masters, which can store up to 16 pending writes. Table entries are allocated on an exclusive read
and table entries are deallocated on a successful write to the same address by any master.
Any exclusive write operation that is not present in the table returns an exclusive fail as acknowledgement
to the operation. If the table is full when the exclusive read is performed, the table replaces a random entry.
Note: When using AXI-exclusive operations, accessing the same location from Avalon-MM interfaces can
result in unpredictable results.

Memory Protection

The single-port controller has address protection to allow the software to configure basic protection of
memory from all masters in the system. If the system has been designed exclusively with AXI masters,
TrustZone
Memory protection is based on physical addresses in memory. You can set rules to allow or disallow accesses
to a range of memory, or to enable only secure accesses to a range of memory (or a combination of the two).
Secure and non-secure regions are specified by rules containing a starting address and ending address with
1 MB boundaries for both addresses. You can override the port defaults and allow or disallow all transactions.
The memory protection table, which is an internal table addressed through the CSR interface, contains rules
to permit or deny memory access. You can configure up to a maximum of twenty rules to control memory
access. The following table lists the fields that you can specify for each rule.
Table 8-4: Fields for Rules in Memory Protection Table
Field
Valid
Port Mask
(1)
TID_low
(1)
TID_high
(1)
Address_
low
SDRAM Controller Subsystem
Send Feedback
28 24
R ( 15 :0 )
®
is supported. Ports that use Avalon-MM can be configured for port level protection.
Width
1 Set to 1 to activate the rule. Set to 0 to deactivate the rule.
10 Specifies the set of ports to which the rule applies, with one bit representing
each port, as follows: bits 0 to 5 correspond to FPGA fabric ports 0 to 5, bit 6
corresponds to AXI L3 switch read, bit 7 is the CPU read, bit 8 is L3 switch
write, and bit 9 is the CPU write.
12 Low transfer ID of the rules to which this rule applies. Incoming transactions
match if they are greater than or equal to this value. Ports with smaller TIDs
have the TID shifted to the lower bits and zero padded at the top.
12 High transfer ID of the rules to which this rule applies. Incoming transactions
match if they are less than or equal to this value.
12 Points to a 1MB block and is the lower address. Incoming addresses match if
they are greater than or equal to this value.
20 16 12
S B ( 2 :0)
Description
AXI-Exclusive Support
8 4 0
C ( 9:0 )
8-13
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