Sdram Controller Address Map And Register Definitions; Document Revision History - Altera Cyclone V Device Handbook

cv_54008
2013.12.30
Figure 8-8: Memory Contents After Executing Example Code

SDRAM Controller Address Map and Register Definitions

The address map and register definitions reside in the hps.html file that accompanies the Hard Processor
System Technical Reference Manual. Click the link at the bottom of this topic to open the file.
To view the module description and base address, scroll to and click the link for the following module
instance:
• sdr
To view the register and field descriptions, scroll to and click the register names. The register addresses are
offsets relative to the base address of each module instance.
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
Base addresses of all HPS modules
• Cyclone V SoC HPS Address Map and Register Definitions
Register and field descriptions for all HPS modules

Document Revision History

Date
December 2013
November 2012
January 2012
SDRAM Controller Subsystem
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Version
2013.12.30 • Added Generating a Preloader Image for HPS with EMIF section.
• Added Debugging HPS SDRAM in the Preloader section.
• Enhanced Simulation section.
1.1 Added address map and register definitions section.
1.0 Initial release.
SDRAM Controller Address Map and Register Definitions
on page 1-1
Changes
8-33
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