Multi-Port Front End - Altera Cyclone V Device Handbook

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Multi-Port Front End

Feature
Low Power Modes
Partial Array Self-
Refresh
ECC
Additive Latency
Write Acknowledg-
ment
User Control of
Memory Controller
Initialization
Controller Bonding
Support
Multi-Port Front End
The multi-port front end (MPFE) and its associated fabric interface provide up to six command ports, four
read-data ports and four write-data ports, through which user logic can access the hard memory controller.
Figure 6-22: Simplified Diagram of the Cyclone V Hard Memory Interface
This figure shows a simplified diagram of the Cyclone V hard memory interface with the MPFE.
Altera Corporation
You can optionally request the controller to put the memory into the self-refresh or
deep power-down modes.
You can select the region of memory to refresh during self-refresh through the mode
register to save power.
Standard Hamming single error correction, double error detection (SECDED) error
correction code (ECC) support:
32 bit data + 8 bit ECC
16 bit data + 8 bit ECC
With additive latency, the controller can issue a READ/WRITE command after the
ACTIVATE command to the bank prior to t
The controller supports write acknowledgment on the local interface.
The controller supports initialization of the memory controller under the control of
user logic—for example, through the software control in the user system if a processor
is present.
You can bond two controllers to achieve wider data width for higher bandwidth
applications.
FPGA
MPFE
Core Logic
Avalon-MM Interface
Description
to increase the command efficiency.
RCD
FPGA
Memory
PHY
Controller
AFI
External Memory Interfaces in Cyclone V Devices
Memory
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2014.01.10