Caches And Memory Interfaces Tab - Altera Nios II User Manual

Chapter 4: Instantiating the Nios II Processor

Caches and Memory Interfaces Tab

1
The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios II
systems can include either an MMU or MPU, but cannot include both an MMU and
MPU in the same design.
f
For information about the Nios II MMU, refer to the
Nios II Processor Reference Handbook.
1
To function correctly with the MMU, the base physical address of all exception vectors
(reset, general exception, break, and fast TLB miss) must point to low physical
memory so that hardware can correctly map their virtual addresses into the kernel
partition. This restriction is enforced by the Nios II Processor parameter editor.
Memory Protection Unit Settings
The Nios II/f core offers a memory protection unit (MPU) to support operating
systems and runtime environments that desire memory protection without the
overhead of virtual memory management. Turning on Include MPU includes the
Nios II MPU in your Nios II hardware system.
1
The Nios II MPU is optional and mutually exclusive from the Nios II MMU. Nios II
systems can include either an MPU or MMU, but cannot include both an MPU and
MMU in the same design.
f
For information about the Nios II MPU, refer to the
Nios II Processor Reference Handbook.
Caches and Memory Interfaces Tab
The Caches and Memory Interfaces tab allows you to configure the cache and
tightly-coupled memory usage for the instruction and data master ports.
Table 4–2. Caches and Memory Interfaces Tab Parameters
Instruction cache
Burst transfers
Number of tightly coupled
instruction master port(s)
Omit data master port
Data cache
Data cache line size
Burst transfers
Data cache victim buffer
implementation
Number of tightly coupled
instruction master port(s)
February 2014 Altera Corporation
Name
Instruction Master
Refer to
Refer to
Programming Model
Programming Model
Description
"Instruction Master Settings" on page
Data Master
"Data Master Settings" on page
Nios II Processor Reference Handbook
4–5
chapter of the
chapter of the
4–6.
4–6.