Sdram Controller Subsystem Interfaces - Altera Cyclone V Device Handbook

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SDRAM Controller Subsystem Interfaces

Figure 8-1: SDRAAM Controller Subsystem High-Level Block Diagram

Interconnect

SDRAM Controller

The SDRAM controller provides high performance data access and run-time programmability. The controller

reorders data to reduce row conflicts and bus turn-around time by grouping read and write transactions

together, allowing for efficient traffic patterns and reduced latency.

The SDRAM controller consists of a multiport front end (MPFE) and a single-port controller. The MPFE

provides multiple independent interfaces to the single-port controller. The single-port controller

communicates with and manages each external memory device.

The MPFE FPGA-to-HPS SDRAM interface port has an asynchronous FIFO buffer followed by a synchronous

FIFO buffer. Both the asynchronous and synchronous FIFO buffers have a read and write data FIFO depth

of 8, and a command FIFO depth of 4. The MPU sub-system 64-bit AXI and L3 interconnect 32-bit AXI

have asynchronous FIFO buffers with read and write data FIFO depth of 8, and command FIFO depth of 4.

For more information, refer to Memory Controller Architecture.

The DDR PHY provides a physical layer interface between the memory controller and memory devices,

which performs read and write memory operations. The DDR PHY has dataflow components, control

components, and calibration logic that handle the calibration for the SDRAM interface timing.

Related Information

Memory Controller Architecture

SDRAM Controller Subsystem Interfaces

The following sections describe the SDRAM controller subsystem interfaces.

Altera Corporation

SDRAM Controller Subsystem

SDRAM Controller

SDRAM Interface

32- to 256-Bit

Control & Status Registers

L4 Peripheral Bus (osc1_clk)

SDRAM Controller Subsystem

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