Altera cyclone V Technical Reference page 1517

17-302
MMC_IPC_Receive_Interrupt
Bit
1
rxipv4herfim
0
rxipv4gfim
MMC_IPC_Receive_Interrupt
This register maintains the interrupts generated when receive IPC statistic counters reach half their
maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and when they cross
their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter
Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Receive
Checksum Offload Interrupt register is 32-bits wide. When the MMC IPC counter that caused the
interrupt is read, its corresponding interrupt bit is cleared. The counter's least-significant byte lane
(bits[7:0]) must be read to clear the interrupt bit.
Module Instance
emac0
emac1
Offset:
0x208
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
Setting this bit masks the interrupt when the rxipv4_
hdrerr_frms counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxipv4_
gd_frms counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Base Address
0xFF700208
0xFF702208
2016.10.28
Access Reset
RW 0x0
RW 0x0
Register Address
Ethernet Media Access Controller
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cv_5v4