Altera cyclone V Technical Reference page 1487

Hard processor system
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17-272
txdeferred
txmulticol_g Fields
Bit
31:0
cnt
txdeferred
Number of successfully transmitted frames after a deferral in Halfduplex mode
Module Instance
emac0
emac1
Offset:
0x154
Access:
RO
31
30
15
14
txdeferred Fields
Bit
31:0
cnt
txlatecol
Number of frames aborted due to late collision error
Module Instance
emac0
emac1
Offset:
0x158
Altera Corporation
Name
Number of successfully transmitted frames after more
than a single collision in Half-duplex mode
29
28
27
26
13
12
11
10
Name
Number of successfully transmitted frames after a
deferral in Halfduplex mode
Description
Base Address
0xFF700000
0xFF702000
Bit Fields
25
24
23
22
cnt
RO 0x0
9
8
7
6
cnt
RO 0x0
Description
Base Address
0xFF700000
0xFF702000
Access
Register Address
0xFF700154
0xFF702154
21
20
19
18
5
4
3
2
Access
Register Address
0xFF700158
0xFF702158
Ethernet Media Access Controller
cv_5v4
2016.10.28
Reset
RO
0x0
17
16
1
0
Reset
RO
0x0
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