Altera cyclone V Technical Reference page 1564

cv_5v4
2016.10.28
31 30
15 14
Layer3_Addr3_Reg2 Fields
Bit
31:0
l3a32
L3_L4_Control3
This register controls the operations of the filter 0 of Layer 3 and Layer 4.
Module Instance
emac0
emac1
Offset:
0x490
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Ethernet Media Access Controller
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29 28 27 26
13 12 11 10
Name
When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in
Register 280 (Layer 3 and Layer 4 Control Register 2),
this field contains the value to be matched with Bits
[127:96] of the IP Source Address field in the IPv6
frames. When Bit 0 (L3PEN2) and Bit 4 (L3DAM2)
are set in Register 280 (Layer 3 and Layer 4 Control
Register 2), this field contains the value to be matched
with Bits [127:96] of the IP Destination Address field
in the IPv6 frames. When Bit 0 (L3PEN2) is reset in
Register 280 (Layer 3 and Layer 4 Control Register 2),
this register is not used.
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
l3a32
RW 0x0
9 8 7 6
l3a32
RW 0x0
Description
Base Address
L3_L4_Control3
21 20 19 18
5 4 3 2
Access
Register Address
0xFF700490
0xFF702490
17-349
17 16
1 0
Reset
RW 0x0
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