Altera cyclone V Technical Reference page 1512

Hard processor system
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cv_5v4
2016.10.28
Bit
28
rxicmpgoim
27
rxtcperoim
26
rxtcpgoim
25
rxudperoim
24
rxudpgoim
Ethernet Media Access Controller
Send Feedback
Name
Setting this bit masks the interrupt when the rxicmp_
gd_octets counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxtcp_
err_octets counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxtcp_
gd_octets counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxudp_
err_octets counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxudp_
gd_octets counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
MMC_IPC_Receive_Interrupt_Mask
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
17-297
Access
Reset
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
Altera Corporation

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