Altera cyclone V Technical Reference page 1593

Hard processor system

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Controls timestamp Pulse-Per-Second output

Module Instance

Altera Corporation

This bit is set when the target time, being

programmed in Target Time Registers, is already

elapsed. This bit is cleared when read by the applica‐

This bit is set high when the auxiliary snapshot is

written to the FIFO.

When set, this bit indicates that the value of system

time is greater or equal to the value specified in the

When set, this bit indicates that the seconds value of

the timestamp (when supporting version 2 format)

has overflowed beyond 32'hFFFF_FFFF.

Base Address

When Read resets

Target Time Elapsed -Reg455 and Reg456

System Time is >= Reg455 and Reg456

System Time is >= Reg455 and Reg456

Seconds Overflow

Ethernet Media Access Controller

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