Altera cyclone V Technical Reference page 1515

17-300
MMC_IPC_Receive_Interrupt_Mask
Bit
11
rxtcperfim
10
rxtcpgfim
9
rxudperfim
8
rxudpgfim
7
rxipv6nopayfim
Altera Corporation
Name
Setting this bit masks the interrupt when the rxtcp_
err_frms counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxtcp_
gd_frms counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxudp_
err_frms counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxudp_
gd_frms counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxipv6_
nopay_frms counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Ethernet Media Access Controller
Send Feedback
cv_5v4