Altera cyclone V Technical Reference page 1464

cv_5v4
2016.10.28
Bit
0
txgboctis
MMC_Receive_Interrupt_Mask
The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when the
receive statistic counters reach half of their maximum value, or maximum value. This register is 32-bits
wide.
Module Instance
emac0
emac1
Offset:
0x10C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
rx512t10 rx256 rx128
23octgbf t511o t255o
im ctgbf ctgbf
im
RW 0x0
RW
0x0 0x0
Ethernet Media Access Controller
Send Feedback
Name
This bit is set when the txoctetcount_gb counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
rx65t rx64o rxosi
127oc ctgbf zegfi
tgbfi im m
im m
RW RW
RW RW 0x0 0x0
0x0
Description
Description
txoctetcount_gb < half max
txoctetcount_gb >= half max
Base Address
Bit Fields
25 24 23 22
rxctr rxrcv rxwdo rxvla
lfim errfi gfim ngbfi
m m
RW RW
0x0 RW 0x0 RW
0x0 0x0
9 8 7 6
rxusi rxjab rxrun rxalg
zegfi erfim tfim nerfi
m m
RW RW
RW 0x0 0x0 RW
0x0 0x0
MMC_Receive_Interrupt_Mask
Access
Register Address
0xFF70010C
0xFF70210C
21 20 19 18
rxfov rxpau rxora rxlen
fim sfim ngefi erfim
m
RW RW RW
0x0 0x0 RW 0x0
0x0
5 4 3 2
rxcrc rxmcg rxbcg rxgoc
erfim fim fim tim
RW RW RW RW
0x0 0x0 0x0 0x0
17-249
Reset
RO 0x0
17 16
rxucg rx1024tm
fim axoctgbf
im
RW
0x0 RW 0x0
1 0
rxgbo rxgbfrmi
ctim m
RW RW 0x0
0x0
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