Altera cyclone V Technical Reference page 1513

17-298
MMC_IPC_Receive_Interrupt_Mask
Bit
23
rxipv6nopayoim
22
rxipv6heroim
21
rxipv6goim
20
rxipv4udsbloim
19
rxipv4fragoim
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Name
Setting this bit masks the interrupt when the rxipv6_
nopay_octets counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks interrupt when the rxipv6_
hdrerr_octets counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxipv6_
gd_octets counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxipv4_
udsbl_octets counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxipv4_
frag_octets counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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