Altera cyclone V Technical Reference page 1569

Hard processor system
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17-354
Layer3_Addr1_Reg3
Layer3_Addr0_Reg3 Fields
Bit
31:0
l3a03
Layer3_Addr1_Reg3
For IPv4 frames, the Layer 3 Address 1 Register 3 contains the 32-bit IP Destination Address field. For
IPv6 frames, it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field.
Module Instance
emac0
emac1
Offset:
0x4A4
Access:
RW
31
30
15
14
Altera Corporation
Name
When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in
Register 292 (Layer 3 and Layer 4 Control Register 3),
this field contains the value to be matched with Bits
[31:0] of the IP Source Address field in the IPv6
frames. When Bit 0 (L3PEN3) and Bit 4 (L3DAM3)
are set in Register 292 (Layer 3 and Layer 4 Control
Register 3), this field contains the value to be matched
with Bits [31:0] of the IP Destination Address field in
the IPv6 frames. When Bit 0 (L3PEN3) is reset and
Bit 2 (L3SAM3) is set in Register 292 (Layer 3 and
Layer 4 Control Register 3), this field contains the
value to be matched with the IP Source Address field
in the IPv4 frames.
29
28
27
26
13
12
11
10
Description
Base Address
0xFF700000
0xFF702000
Bit Fields
25
24
23
22
l3a13
RW 0x0
9
8
7
6
l3a13
RW 0x0
Access
Register Address
0xFF7004A4
0xFF7024A4
21
20
19
18
5
4
3
2
Ethernet Media Access Controller
cv_5v4
2016.10.28
Reset
RW
0x0
17
16
1
0
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