Altera cyclone V Technical Reference page 1550

cv_5v4
2016.10.28
Layer3_Addr3_Reg0 Fields
Bit
31:0
l3a30
L3_L4_Control1
This register controls the operations of the filter 0 of Layer 3 and Layer 4.
Module Instance
emac0
emac1
Offset:
0x430
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
l3hdbm1
RW 0x0
Ethernet Media Access Controller
Send Feedback
Name
When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in
Register 256 (Layer 3 and Layer 4 Control Register 0),
this field contains the value to be matched with Bits
[127:96] of the IP Source Address field in the IPv6
frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0)
are set in Register 256 (Layer 3 and Layer 4 Control
Register 0), this field contains the value to be matched
with Bits [127:96] of the IP Destination Address field
in the IPv6 frames. When Bit 0 (L3PEN0) is reset in
Register 256 (Layer 3 and Layer 4 Control Register 0),
this register is not used.
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
Description
Base Address
Bit Fields
25 24 23 22
9 8 7 6
l3hsbm1
RW 0x0
L3_L4_Control1
Access
Register Address
0xFF700430
0xFF702430
21 20 19 18
l4dpi l4dpm l4spi l4spm
m1 1 m1 1
RW RW RW RW
0x0 0x0 0x0 0x0
5 4 3 2
l3dai l3dam l3sai l3sam
m1 1 m1 1
RW RW RW RW
0x0 0x0 0x0 0x0
17-335
Reset
RW 0x0
17 16
Reser l4pen1
ved
RW 0x0
1 0
Reser l3pen1
ved
RW 0x0
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