Altera cyclone V Technical Reference page 1543

17-328
L3_L4_Control0
31 30
15 14
l3hdbm0
RW 0x0
L3_L4_Control0 Fields
Bit
21
l4dpim0
20
l4dpm0
19
l4spim0
18
l4spm0
16
l4pen0
Altera Corporation
29 28 27 26
Reserved
13 12 11 10
Name
When set, this bit indicates that the Layer 4 Destina‐
tion Port number field is enabled for inverse
matching. When reset, this bit indicates that the Layer
4 Destination Port number field is enabled for perfect
matching. This bit is valid and applicable only when
Bit 20 (L4DPM0) is set high.
When set, this bit indicates that the Layer 4 Destina‐
tion Port number field is enabled for matching. When
reset, the MAC ignores the Layer 4 Destination Port
number field for matching.
When set, this bit indicates that the Layer 4 Source
Port number field is enabled for inverse matching.
When reset, this bit indicates that the Layer 4 Source
Port number field is enabled for perfect matching.
This bit is valid and applicable only when Bit 18
(L4SPM0) is set high.
When set, this bit indicates that the Layer 4 Source
Port number field is enabled for matching. When
reset, the MAC ignores the Layer 4 Source Port
number field for matching.
When set, this bit indicates that the Source and
Destination Port number fields for UDP frames are
used for matching. When reset, this bit indicates that
the Source and Destination Port number fields for
TCP frames are used for matching. The Layer 4
matching is done only when either L4SPM0 or
L4DPM0 bit is set high.
Bit Fields
25 24 23 22
9 8 7 6
l3hsbm0
RW 0x0
Description
21 20 19 18
l4dpi l4dpm l4spi l4spm
m0 0 m0 0
RW RW RW RW
0x0 0x0 0x0 0x0
5 4 3 2
l3dai l3dam l3sai l3sam
m0 0 m0 0
RW RW RW RW
0x0 0x0 0x0 0x0
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
Reser l4pen0
ved
RW 0x0
1 0
Reser l3pen0
ved
RW 0x0
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Send Feedback