Altera cyclone V Technical Reference page 1590

cv_5v4
2016.10.28
Module Instance
emac0
emac1
Offset:
0x720
Access:
RW
31 30
trgtbusy
RO 0x0
15 14
Target_Time_Nanoseconds Fields
Bit
31
trgtbusy
30:0
ttslo
Ethernet Media Access Controller
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0xFF700000
0xFF702000
29 28 27 26
13 12 11 10
Name
The MAC sets this bit when the PPSCMD field
(Bits[3:0]) in Register 459 (PPS Control Register) is
programmed to 010 or 011. Programming the
PPSCMD field to 010 or 011, instructs the MAC to
synchronize the Target Time Registers to the PTP
clock domain. The MAC clears this bit after synchro‐
nizing the Target Time Registers to the PTP clock
domain The application must not update the Target
Time Registers when this bit is read as 1. Otherwise,
the synchronization of the previous programmed
time gets corrupted. This bit is reserved when the
Enable Flexible Pulse-Per-Second Output feature is
not selected.
This register stores the time in (signed) nanoseconds.
When the value of the timestamp matches the both
Target Timestamp registers, then based on the
TRGTMODSEL0 field (Bits [6:5]) in Register 459
(PPS Control Register), the MAC starts or stops the
PPS signal output and generates an interrupt (if
enabled). This value should not exceed 0x3B9A_C9FF
when TSCTRLSSR is set in the Timestamp control
register. The actual start or stop time of the PPS signal
output may have an error margin up to one unit of
sub-second increment value.
Base Address
Bit Fields
25 24 23 22
ttslo
RW 0x0
9 8 7 6
ttslo
RW 0x0
Description
Target_Time_Nanoseconds
Register Address
0xFF700720
0xFF702720
21 20 19 18
5 4 3 2
Access
17-375
17 16
1 0
Reset
RO 0x0
RW 0x0
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