Altera cyclone V Technical Reference page 1511

17-296
MMC_IPC_Receive_Interrupt_Mask
MMC_IPC_Receive_Interrupt_Mask
This register maintains the mask for the interrupt generated from the receive IPC statistic counters.
Module Instance
emac0
emac1
Offset:
0x200
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved rxicm
peroi
15 14
Reserved rxicm
perfi
MMC_IPC_Receive_Interrupt_Mask Fields
Bit
29
rxicmperoim
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
rxicm rxtcp rxtcp
pgoim eroim goim
m
RW RW RW
RW 0x0 0x0 0x0
0x0
13 12 11 10
rxicm rxtcp rxtcp
pgfim erfim gfim
m
RW RW RW
RW 0x0 0x0 0x0
0x0
Name
Setting this bit masks the interrupt when the rxicmp_
err_octets counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
rxudp rxudp rxipv rxipv
eroim goim 6nopa 6hero
yoim im
RW RW
0x0 0x0 RW RW
0x0 0x0
9 8 7 6
rxudp rxudp rxipv rxipv
erfim gfim 6nopa 6herf
yfim im
RW RW
0x0 0x0 RW RW
0x0 0x0
Description
Description
counter < half max
counter >= half max or max
Register Address
0xFF700200
0xFF702200
21 20 19 18
rxipv rxipv rxipv rxipv
6goim 4udsb 4frag 4nopa
loim oim yoim
RW
0x0 RW RW RW
0x0 0x0 0x0
5 4 3 2
rxipv rxipv rxipv rxipv
6gfim 4udsb 4frag 4nopa
lfim fim yfim
RW
0x0 RW RW RW
0x0 0x0 0x0
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
rxipv rxipv4go
4hero im
im
RW 0x0
RW
0x0
1 0
rxipv rxipv4gf
4herf im
im
RW 0x0
RW
0x0
Access Reset
RW 0x0
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