Altera cyclone V Technical Reference page 1582

Hard processor system

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Ethernet Media Access Controller

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When set, the Timestamp Low register rolls over after

0x3B9A_C9FF value (that is, 1 nanosecond accuracy)

and increments the timestamp (High) seconds. When

reset, the rollover value of sub-second register is

0x7FFF_FFFF. The sub-second increment has to be

programmed correctly depending on the PTP

reference clock frequency and the value of this bit.

When set, the timestamp snapshot is enabled for all

frames received by the MAC.

When set, the content of the Timestamp Addend

correction. This is cleared when the update is

completed. This register bit should be zero before

When set, the timestamp interrupt is generated when

the System Time becomes greater than the value

written in the Target Time register. This bit is reset

after the generation of the Timestamp Trigger

Timestamp Low register rolls over at

Timestamp Low register rolls over at 1ns

Timestamp snapshot disabled

Timestamp snapshot enabled

Timestamp Addend register is not updated

Timestamp Addend register is updated

Timestamp not generated

Timestamp generated

Timestamp_Control

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