Altera cyclone V Technical Reference page 1583

17-368
Timestamp_Control
Bit
3
tsupdt
2
tsinit
1
tscfupdt
Altera Corporation
Name
When set, the system time is updated (added or
subtracted) with the value specified in Register 452
(System Time - Seconds Update Register) and
Register 453 (System Time - Nanoseconds Update
Register). This bit should be read zero before
updating it. This bit is reset when the update is
completed in hardware. The Timestamp Higher Word
register is not updated.
Value
0x0
0x1
When set, the system time is initialized (overwritten)
with the value specified in the Register 452 (System
Time - Seconds Update Register) and Register 453
(System Time - Nanoseconds Update Register). This
bit should be read zero before updating it. This bit is
reset when the initialization is complete. The
Timestamp Higher Word register can only be initial‐
ized.
Value
0x0
0x1
When set, this bit indicates that the system times
update should be done using the fine update method.
When reset, it indicates the system timestamp update
should be done using the Coarse method.
Value
0x0
0x1
Description
Description
Timestamp not updated (added or
subtracted) with values in Register 452 and
Register 453
Timestamp updated (added or subtracted)
with values in Register 452 and Register 453
Description
Timestamp not initialized (overwritten) by
values in Register 452 and Register 453
Timestamp initialized (overwritten) by values
in Register 452 and Register 453
Description
Timestamp Coarse
Timestamp Fine
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
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