Altera cyclone V Technical Reference page 1545

17-330
Layer4_Address0
Bit
2
l3sam0
0
l3pen0
Layer4_Address0
Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian
mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you
should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four
clock cycles delay of the destination clock.
Module Instance
emac0
emac1
Offset:
0x404
Access:
RW
31 30
15 14
Altera Corporation
Name
When set, this bit indicates that the Layer 3 IP Source
Address field is enabled for matching. When reset, the
MAC ignores the Layer 3 IP Source Address field for
matching. Note: When Bit 0 (L3PEN0) is set, you
should set either this bit or Bit 4 (L3DAM0) because
either IPv6 SA or DA can be checked for filtering.
When set, this bit indicates that the Layer 3 IP Source
or Destination Address matching is enabled for the
IPv6 frames. When reset, this bit indicates that the
Layer 3 IP Source or Destination Address matching is
enabled for the IPv4 frames. The Layer 3 matching is
done only when either L3SAM0 or L3DAM0 bit is set
high.
29 28 27 26
13 12 11 10
Description
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
l4dp0
RW 0x0
9 8 7 6
l4sp0
RW 0x0
Access
Register Address
0xFF700404
0xFF702404
21 20 19 18
5 4 3 2
Ethernet Media Access Controller
cv_5v4
2016.10.28
Reset
RW 0x0
RW 0x0
17 16
1 0
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