Altera cyclone V Technical Reference page 1516

cv_5v4
2016.10.28
Bit
6
rxipv6herfim
5
rxipv6gfim
4
rxipv4udsblfim
3
rxipv4fragfim
2
rxipv4nopayfim
Ethernet Media Access Controller
Send Feedback
Name
Setting this bit masks the interrupt when the rxipv6_
hdrerr_frms counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxipv6_
gd_frms counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxipv4_
udsbl_frms counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxipv4_
frag_frms counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the rxipv4_
nopay_frms counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
MMC_IPC_Receive_Interrupt_Mask
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
17-301
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Altera Corporation