Altera cyclone V Technical Reference page 1544

Hard processor system
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cv_5v4
2016.10.28
Bit
15:11
l3hdbm0
10:6
l3hsbm0
5
l3daim0
4
l3dam0
3
l3saim0
Ethernet Media Access Controller
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Name
IPv4 Frames: This field contains the number of higher
bits of IP Destination Address that are matched in the
IPv4 frames. The following list describes the values of
this field: * 0: No bits are masked. * 1: LSb[0] is
masked. * 2: Two LSbs [1:0] are masked. * ... * 31: All
bits except MSb are masked. IPv6 Frames: Bits [12:11]
of this field correspond to Bits [6:5] of L3HSBM0,
which indicate the number of lower bits of IP Source
or Destination Address that are masked in the IPv6
frames. The following list describes the concatenated
values of the L3HDBM0[1:0] and L3HSBM0 bits: * 0:
No bits are masked. * 1: LSb[0] is masked. * 2: Two
LSbs [1:0] are masked. * ... * 127: All bits except MSb
are masked. This field is valid and applicable only if
L3DAM0 or L3SAM0 is set high.
IPv4 Frames: This field contains the number of lower
bits of IP Source Address that are masked for
matching in the IPv4 frames. The following list
describes the values of this field: * 0: No bits are
masked. * 1: LSb[0] is masked. * 2: Two LSbs [1:0] are
masked. * ... * 31: All bits except MSb are masked.
IPv6 Frames: This field contains Bits [4:0] of the field
that indicates the number of higher bits of IP Source
or Destination Address matched in the IPv6 frames.
This field is valid and applicable only if L3DAM0 or
L3SAM0 is set high.
When set, this bit indicates that the Layer 3 IP
Destination Address field is enabled for inverse
matching. When reset, this bit indicates that the Layer
3 IP Destination Address field is enabled for perfect
matching. This bit is valid and applicable only when
Bit 4 (L3DAM0) is set high.
When set, this bit indicates that Layer 3 IP Destina‐
tion Address field is enabled for matching. When
reset, the MAC ignores the Layer 3 IP Destination
Address field for matching. Note: When Bit 0
(L3PEN0) is set, you should set either this bit or Bit 2
(L3SAM0) because either IPv6 DA or SA can be
checked for filtering.
When set, this bit indicates that the Layer 3 IP Source
Address field is enabled for inverse matching. When
reset, this bit indicates that the Layer 3 IP Source
Address field is enabled for perfect matching. This bit
is valid and applicable only when Bit 2 (L3SAM0) is
set high.
Description
17-329
L3_L4_Control0
Access
Reset
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
Altera Corporation

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