Altera cyclone V Technical Reference page 1599

17-384
PPS0_Width
31 30
15 14
PPS0_Interval Fields
Bit
31:0
ppsint
PPS0_Width
The PPS0 Width register contains the number of units of sub-second increment value between the rising
and corresponding falling edges of the PPS0 signal output (ptp_pps_o[0]).
Module Instance
emac0
emac1
Offset:
0x764
Access:
RW
31 30
15 14
Altera Corporation
29 28 27 26
13 12 11 10
Name
These bits store the interval between the rising edges
of PPS0 signal output in terms of units of sub-second
increment value. You need to program one value less
than the required interval. For example, if the PTP
reference clock is 50 MHz (period of 20ns), and
desired interval between rising edges of PPS0 signal
output is 100ns (that is, five units of sub-second
increment value), then you should program value 4 (5
-1) in this register.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
ppsint
RW 0x0
9 8 7 6
ppsint
RW 0x0
Description
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
ppswidth
RW 0x0
9 8 7 6
ppswidth
RW 0x0
21 20 19 18
5 4 3 2
Access
Register Address
0xFF700764
0xFF702764
21 20 19 18
5 4 3 2
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
17 16
1 0
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