Altera cyclone V Technical Reference page 1558

cv_5v4
2016.10.28
L3_L4_Control2 Fields
Bit
21
l4dpim2
20
l4dpm2
19
l4spim2
18
l4spm2
16
l4pen2
15:11
l3hdbm2
Ethernet Media Access Controller
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Name
When set, this bit indicates that the Layer 4 Destina‐
tion Port number field is enabled for inverse
matching. When reset, this bit indicates that the Layer
4 Destination Port number field is enabled for perfect
matching. This bit is valid and applicable only when
Bit 20 (L4DPM0) is set high.
When set, this bit indicates that the Layer 4 Destina‐
tion Port number field is enabled for matching. When
reset, the MAC ignores the Layer 4 Destination Port
number field for matching.
When set, this bit indicates that the Layer 4 Source
Port number field is enabled for inverse matching.
When reset, this bit indicates that the Layer 4 Source
Port number field is enabled for perfect matching.
This bit is valid and applicable only when Bit 18
(L4SPM2) is set high.
When set, this bit indicates that the Layer 4 Source
Port number field is enabled for matching. When
reset, the MAC ignores the Layer 4 Source Port
number field for matching.
When set, this bit indicates that the Source and
Destination Port number fields for UDP frames are
used for matching. When reset, this bit indicates that
the Source and Destination Port number fields for
TCP frames are used for matching. The Layer 4
matching is done only when either L4SPM2 or
L4DPM2 bit is set high.
IPv4 Frames: This field contains the number of higher
bits of IP Destination Address that are matched in the
IPv4 frames. The following list describes the values of
this field: * 0: No bits are masked. * 1: LSb[0] is
masked. * 2: Two LSbs [1:0] are masked. * ... * 31: All
bits except MSb are masked. IPv6 Frames: Bits [12:11]
of this field correspond to Bits [6:5] of L3HSBM2,
which indicate the number of lower bits of IP Source
or Destination Address that are masked in the IPv6
frames. The following list describes the concatenated
values of the L3HDBM2[1:0] and L3HSBM2 bits: * 0:
No bits are masked. * 1: LSb[0] is masked. * 2: Two
LSbs [1:0] are masked. * ... * 127: All bits except MSb
are masked. This field is valid and applicable only if
L3DAM2 or L3SAM2 is set high.
Description
17-343
L3_L4_Control2
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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