Altera cyclone V Technical Reference page 1523

Hard processor system
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17-308
rxipv4_gd_frms
Bit
4
rxipv4udsblfis
3
rxipv4fragfis
2
rxipv4nopayfis
1
rxipv4herfis
0
rxipv4gfis
rxipv4_gd_frms
Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload
Altera Corporation
Name
This bit is set when the rxipv4_udsbl_frms counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv4_frag_frms counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv4_nopay_frms counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv4_hdrerr_frms counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv4_gd_frms counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
2016.10.28
Access
Reset
RO
0x0
RO
0x0
RO
0x0
RO
0x0
RO
0x0
Ethernet Media Access Controller
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