Altera cyclone V Technical Reference page 1592

Hard processor system

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Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Timestamp_Status Fields

Ethernet Media Access Controller

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software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

This field indicates the number of Snapshots available

in the FIFO. A value of 16 (equal to the depth of the

FIFO) indicates that the Auxiliary Snapshot FIFO is

full. These bits are cleared (to 00000) when the

Auxiliary snapshot FIFO clear bit is set.

This bit is set when the Auxiliary timestamp snapshot

FIFO is full and external trigger was set. This

indicates that the latest snapshot is not stored in the

These bits identify the Auxiliary trigger inputs for

which the timestamp available in the Auxiliary

Snapshot Register is applicable. When more than one

bit is set at the same time, it means that

corresponding auxiliary triggers were sampled at the

same clock. These bits are applicable only if the

number of Auxiliary snapshots is more than one. One

bit is assigned for each trigger as shown in the

following list: * Bit 16: Auxiliary trigger 0 * Bit 17:

Auxiliary trigger 1 * Bit 18: Auxiliary trigger 2 * Bit

19: Auxiliary trigger 3 The software can read this

timestamp is taken.

Aux timestamp snapshot full

Timestamp_Status

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