Altera cyclone V Technical Reference page 1561

17-346
Layer3_Addr0_Reg2
Layer3_Addr0_Reg2
For IPv4 frames, the Layer 3 Address 0 Register 2 contains the 32-bit IP Source Address field. For IPv6
frames, it contains Bits [31:0] of the 128-bit IP Source Address or Destination Address field.
Module Instance
emac0
emac1
Offset:
0x470
Access:
RW
31 30
15 14
Layer3_Addr0_Reg2 Fields
Bit
31:0
l3a02
Layer3_Addr1_Reg2
For IPv4 frames, the Layer 3 Address 1 Register 2 contains the 32-bit IP Destination Address field. For
IPv6 frames, it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field.
Module Instance
emac0
Altera Corporation
29 28 27 26
13 12 11 10
Name
When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in
Register 280 (Layer 3 and Layer 4 Control Register 2),
this field contains the value to be matched with Bits
[31:0] of the IP Source Address field in the IPv6
frames. When Bit 0 (L3PEN2) and Bit 4 (L3DAM2)
are set in Register 280 (Layer 3 and Layer 4 Control
Register 2), this field contains the value to be matched
with Bits [31:0] of the IP Destination Address field in
the IPv6 frames. When Bit 0 (L3PEN2) is reset and
Bit 2 (L3SAM2) is set in Register 280 (Layer 3 and
Layer 4 Control Register 2), this field contains the
value to be matched with the IP Source Address field
in the IPv4 frames.
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
l3a02
RW 0x0
9 8 7 6
l3a02
RW 0x0
Description
Base Address
0xFF700000
Register Address
0xFF700470
0xFF702470
21 20 19 18
5 4 3 2
Access
Register Address
0xFF700474
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
Send Feedback