Altera cyclone V Technical Reference page 1519

Hard processor system
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17-304
MMC_IPC_Receive_Interrupt
Bit
26
rxtcpgois
25
rxudperois
24
rxudpgois
23
rxipv6nopayois
22
rxipv6herois
Altera Corporation
Name
This bit is set when the rxtcp_gd_octets counter
reaches half the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxudp_err_octets counter
reaches half the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxudp_gd_octets counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv6_nopay_octets counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv6_hdrerr_octets counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
2016.10.28
Access
Reset
RO
0x0
RO
0x0
RO
0x0
RO
0x0
RO
0x0
Ethernet Media Access Controller
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cv_5v4

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