Altera cyclone V Technical Reference page 1589

17-374
Target_Time_Seconds
Timestamp_Addend Fields
Bit
31:0
tsar
Target_Time_Seconds
The Target Time Seconds register, along with Target Time Nanoseconds register, is used to schedule an
interrupt event (Register 458[1] when Advanced Timestamping is enabled; otherwise, TS interrupt bit in
Register14[9]) when the system time exceeds the value programmed in these registers.
Module Instance
emac0
emac1
Offset:
0x71C
Access:
RW
31 30
15 14
Target_Time_Seconds Fields
Bit
31:0
tstr
Target_Time_Nanoseconds
Target time
Altera Corporation
Name
This field indicates the 32-bit time value to be added
to the Accumulator register to achieve time synchro‐
nization.
29 28 27 26
13 12 11 10
Name
This register stores the time in seconds. When the
timestamp value matches or exceeds both Target
Timestamp registers, then based on Bits [6:5] of
Register 459 (PPS Control Register), the MAC starts
or stops the PPS signal output and generates an
interrupt (if enabled).
Description
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
tstr
RW 0x0
9 8 7 6
tstr
RW 0x0
Description
Access
Register Address
0xFF70071C
0xFF70271C
21 20 19 18
5 4 3 2
Access
Ethernet Media Access Controller
cv_5v4
2016.10.28
Reset
RW 0x0
17 16
1 0
Reset
RW 0x0
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