Altera cyclone V Technical Reference page 1562

cv_5v4
2016.10.28
Module Instance
emac1
Offset:
0x474
Access:
RW
31 30
15 14
Layer3_Addr1_Reg2 Fields
Bit
31:0
l3a12
Layer3_Addr2_Reg2
For IPv4 frames, the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames, it contains Bits [95:64] of
the 128-bit IP Source Address or Destination Address field.
Module Instance
emac0
emac1
Offset:
0x478
Ethernet Media Access Controller
Send Feedback
0xFF702000
29 28 27 26
13 12 11 10
Name
Layer 3 Address 1 Field When Bit 0 (L3PEN2) and Bit
2 (L3SAM2) are set in Register 280 (Layer 3 and
Layer 4 Control Register 2), this field contains the
value to be matched with Bits [63:32] of the IP Source
Address field in the IPv6 frames. When Bit 0
(L3PEN2) and Bit 4 (L3DAM2) are set in Register 280
(Layer 3 and Layer 4 Control Register 2), this field
contains the value to be matched with Bits [63:32] of
the IP Destination Address field in the IPv6 frames.
When Bit 0 (L3PEN2) is reset and Bit 4 (L3DAM2) is
set in Register 280 (Layer 3 and Layer 4 Control
Register 2), this field contains the value to be matched
with the IP Destination Address field in the IPv4
frames.
0xFF700000
0xFF702000
Base Address
Bit Fields
25 24 23 22
l3a12
RW 0x0
9 8 7 6
l3a12
RW 0x0
Description
Base Address
Layer3_Addr2_Reg2
Register Address
0xFF702474
21 20 19 18
5 4 3 2
Access
Register Address
0xFF700478
0xFF702478
17-347
17 16
1 0
Reset
RW 0x0
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