Altera cyclone V Technical Reference page 1475

Hard processor system
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17-260
MMC_Transmit_Interrupt_Mask
Bit
5
tx65t127octgbfim
4
tx64octgbfim
3
txmcgfim
2
txbcgfim
1
txgbfrmim
Altera Corporation
Name
Setting this bit masks the interrupt when the
tx65to127octets_gb counter reaches half of the
maximum value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the
tx64octets_gb counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the txmulti‐
castframes_g counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the txbroad‐
castframes_g counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the txframe‐
count_gb counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
2016.10.28
Access
Reset
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
Ethernet Media Access Controller
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cv_5v4

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