Altera cyclone V Technical Reference page 1467

17-252
MMC_Receive_Interrupt_Mask
Bit
15
rx512t1023octgbfim
14
rx256t511octgbfim
13
rx128t255octgbfim
12
rx65t127octgbfim
11
rx64octgbfim
Altera Corporation
Name
Setting this bit masks the interrupt when the
rx512to1023octets_gb counter reaches half of the
maximum value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the
rx256to511octets_gb counter reaches half of the
maximum value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the
rx128to255octets_gb counter reaches half of the
maximum value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the
rx65to127octets_gb counter reaches half of the
maximum value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the
rx64octets_gb counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Ethernet Media Access Controller
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