Altera cyclone V Technical Reference page 1471

Hard processor system
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17-256
MMC_Transmit_Interrupt_Mask
MMC_Transmit_Interrupt_Mask Fields
Bit
25
txosizegfim
24
txvlangfim
23
txpausfim
22
txexdeffim
21
txgfrmim
Altera Corporation
Name
Setting this bit masks the interrupt when the
txoversize_g counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the
txvlanframes_g counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the txpause‐
frames counter reaches half of the maximum value or
the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the
txexcessdef counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the txframe‐
count_g counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
2016.10.28
Access
Reset
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
Ethernet Media Access Controller
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cv_5v4

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