Altera cyclone V Technical Reference page 1572

cv_5v4
2016.10.28
Layer3_Addr3_Reg3 Fields
Bit
31:0
l3a33
Hash_Table_Reg0
This register contains the first 32 bits of the hash table. The 256-bit Hash table is used for group address
filtering. For hash filtering, the content of the destination address in the incoming frame is passed through
the CRC logic and the upper eight bits of the CRC register are used to index the content of the Hash table.
The most significant bits determines the register to be used (Hash Table Register X), and the least
significant five bits determine the bit within the register. For example, a hash value of 8b'10111111 selects
Bit 31 of the Hash Table Register 5. The hash value of the destination address is calculated in the following
way: 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate
CRC32). 2. Perform bitwise reversal for the value obtained in Step 1. 3. Take the upper 8 bits from the
value obtained in Step 2. If the corresponding bit value of the register is 1'b1, the frame is accepted.
Otherwise, it is rejected. If the Bit 1 (Pass All Multicast) is set in Register 1 (MAC Frame Filter), then all
multicast frames are accepted regardless of the multicast hash values. Because the Hash Table register is
double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24]
(in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are
written. Note: Because of double-synchronization, consecutive writes to this register should be performed
after at least four clock cycles in the destination clock domain.
Module Instance
emac0
emac1
Offset:
0x500
Access:
RW
Ethernet Media Access Controller
Send Feedback
Name
When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in
Register 292 (Layer 3 and Layer 4 Control Register 3),
this field contains the value to be matched with Bits
[127:96] of the IP Source Address field in the IPv6
frames. When Bit 0 (L3PEN3) and Bit 4 (L3DAM3)
are set in Register 292 (Layer 3 and Layer 4 Control
Register 3), this field contains the value to be matched
with Bits [127:96] of the IP Destination Address field
in the IPv6 frames. When Bit 0 (L3PEN3) is reset in
Register 292 (Layer 3 and Layer 4 Control Register 3),
this register is not used.
0xFF700000
0xFF702000
Description
Base Address
0xFF700500
0xFF702500
17-357
Hash_Table_Reg0
Access Reset
RW 0x0
Register Address
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