Altera cyclone V Technical Reference page 1584

cv_5v4
2016.10.28
Bit
0
tsena
Sub_Second_Increment
In the Coarse Update mode (TSCFUPDT bit in Register 448), the value in this register is added to the
system time every clock cycle of clk_ptp_ref_i. In the Fine Update mode, the value in this register is added
to the system time whenever the Accumulator gets an overflow.
Module Instance
emac0
emac1
Offset:
0x704
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Ethernet Media Access Controller
Send Feedback
Name
When set, the timestamp is added for the transmit
and receive frames. When disabled, timestamp is not
added for the transmit and receive frames and the
Timestamp Generator is also suspended. You need to
initialize the Timestamp (system time) after enabling
this mode. On the receive side, the MAC processes
the 1588 frames only if this bit is set.
Value
0x0
0x1
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Description
Timestamp not added
Timestamp added for transmit and receive
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Sub_Second_Increment
Access
Register Address
0xFF700704
0xFF702704
21 20 19 18
5 4 3 2
ssinc
RW 0x0
17-369
Reset
RW 0x0
17 16
1 0
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