Altera cyclone V Technical Reference page 1520

Hard processor system
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cv_5v4
2016.10.28
Bit
21
rxipv6gois
20
rxipv4udsblois
19
rxipv4fragois
18
rxipv4nopayois
17
rxipv4herois
Ethernet Media Access Controller
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Name
This bit is set when the rxipv6_gd_octets counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv4_udsbl_octets counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv4_frag_octets counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv4_nopay_octets counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
This bit is set when the rxipv4_hdrerr_octets counter
reaches half of the maximum value or the maximum
value.
Value
0x0
0x1
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
MMC_IPC_Receive_Interrupt
Access
RO
RO
RO
RO
RO
Altera Corporation
17-305
Reset
0x0
0x0
0x0
0x0
0x0

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