Altera cyclone V Technical Reference page 1470

cv_5v4
2016.10.28
Bit
0
rxgbfrmim
MMC_Transmit_Interrupt_Mask
The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the
transmit statistic counters reach half of their maximum value or maximum value. This register is 32-bits
wide.
Module Instance
emac0
emac1
Offset:
0x110
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
txmcolgf txsco txufl
im lgfim owerf
RW 0x0 RW
0x0
0x0
Ethernet Media Access Controller
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Name
Setting this bit masks the interrupt when the rxframe‐
count_gb counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
txbcg txmcg txucg
bfim bfim bfim
im
RW RW RW
RW 0x0 0x0 0x0
Description
Description
counter < half max
counter >= half max or max
Base Address
Bit Fields
25 24 23 22
txosi txvla txpau txexd
zegfi ngfim sfim effim
m
RW RW RW
RW 0x0 0x0 0x0
0x0
9 8 7 6
tx102 tx512 tx256 tx128
4tmax t1023 t511o t255o
octgb octgb ctgbf ctgbf
fim fim im im
RW RW RW RW
0x0 0x0 0x0 0x0
MMC_Transmit_Interrupt_Mask
Access
Register Address
0xFF700110
0xFF702110
21 20 19 18
txgfr txgoc txcar txexc
mim tim erfim olfim
RW RW RW RW
0x0 0x0 0x0 0x0
5 4 3 2
tx65t tx64o txmcg txbcg
127oc ctgbf fim fim
tgbfi im
RW RW
m
RW 0x0 0x0
RW 0x0
0x0
17-255
Reset
RW 0x0
17 16
txlat txdeffim
colfi
RW 0x0
m
RW
0x0
1 0
txgbf txgbocti
rmim m
RW RW 0x0
0x0
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