Altera cyclone V Technical Reference page 1588

cv_5v4
2016.10.28
System_Time_Nanoseconds_Update Fields
Bit
31
addsub
30:0
tsss
Timestamp_Addend
This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit
in Register 448). This register content is added to a 32-bit accumulator in every clock cycle (of
clk_ptp_ref_i) and the system time is updated whenever the accumulator overflows.
Module Instance
emac0
emac1
Offset:
0x718
Access:
RW
31 30
15 14
Ethernet Media Access Controller
Send Feedback
Name
When this bit is set, the time value is subtracted with
the contents of the update register. When this bit is
reset, the time value is added with the contents of the
update register.
Value
0x0
0x1
The value in this field has the sub second representa‐
tion of time, with an accuracy of 0.46 ns. When bit 9
(TSCTRLSSR) is set in Register 448 (Timestamp
Control Register), each bit represents 1 ns and the
programmed value should not exceed 0x3B9A_C9FF.
0xFF700000
0xFF702000
29 28 27 26
13 12 11 10
Description
Description
Add Time Value from update reg
Subtract Time Value of update reg
Base Address
Bit Fields
25 24 23 22
tsar
RW 0x0
9 8 7 6
tsar
RW 0x0
Timestamp_Addend
Access
Register Address
0xFF700718
0xFF702718
21 20 19 18
5 4 3 2
17-373
Reset
RW 0x0
RW 0x0
17 16
1 0
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