Altera cyclone V Technical Reference page 1579

17-364
Timestamp_Control
Module Instance
emac0
emac1
Offset:
0x700
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
tsmstren tsevn tsipv
a tena 4ena
RW 0x0 RW
0x0
Timestamp_Control Fields
Bit
25
atsen0
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
tsipv tsipe tsver
6ena na 2ena
RW RW RW RW
0x1 0x0 0x0 0x0
Name
This field controls capturing the Auxiliary Snapshot
Trigger 0. When this bit is set, the Auxiliary snapshot
of event on ptp_aux_trig_i[0] input is enabled. When
this bit is reset, the events on this input are ignored.
Value
0x0
0x1
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
atsen atsfc
0
RW
RW 0x0
0x0
9 8 7 6
tsctr tsena Reserved
lssr ll
RW RW
0x0 0x0
Description
Description
Auxiliary snapshot of event on ptp_aux_trig_
i[0] input is disabled.
Auxiliary snapshot of event on ptp_aux_trig_
i[0] input is enabled.
Register Address
0xFF700700
0xFF702700
21 20 19 18
Reserved tsenm
acadd
r
RW
0x0
5 4 3 2
tsadd tstri tsupd tsini
reg g t t
RW RW RW RW
0x0 0x0 0x0 0x0
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
snaptypsel
RW 0x0
1 0
tscfu tsena
pdt
RW 0x0
RW
0x0
Access Reset
RW 0x0
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