Altera cyclone V Technical Reference page 1560

cv_5v4
2016.10.28
Layer4_Address2
Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian
mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you
should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four
clock cycles delay of the destination clock.
Module Instance
emac0
emac1
Offset:
0x464
Access:
RW
31 30
15 14
Layer4_Address2 Fields
Bit
31:16
l4dp2
15:0
l4sp2
Ethernet Media Access Controller
Send Feedback
0xFF700000
0xFF702000
29 28 27 26
13 12 11 10
Name
When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2)
is set in Register 280 (Layer 3 and Layer 4 Control
Register 2), this field contains the value to be matched
with the TCP Destination Port Number field in the
IPv4 or IPv6 frames. When Bit 16 (L4PEN2) and Bit
20 (L4DPM2) are set in Register 280 (Layer 3 and
Layer 4 Control Register 2), this field contains the
value to be matched with the UDP Destination Port
Number field in the IPv4 or IPv6 frames.
When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2)
is set in Register 280 (Layer 3 and Layer 4 Control
Register 2), this field contains the value to be matched
with the TCP Source Port Number field in the IPv4 or
IPv6 frames. When Bit 16 (L4PEN2) and Bit 20
(L4DPM2) are set in Register 280 (Layer 3 and Layer
4 Control Register 2), this field contains the value to
be matched with the UDP Source Port Number field
in the IPv4 or IPv6 frames.
Base Address
Bit Fields
25 24 23 22
l4dp2
RW 0x0
9 8 7 6
l4sp2
RW 0x0
Description
Layer4_Address2
Register Address
0xFF700464
0xFF702464
21 20 19 18
5 4 3 2
Access
17-345
17 16
1 0
Reset
RW 0x0
RW 0x0
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